This invention relates to an insulated-gate field-effect transistor in which interdigitated source and drain fingers of one conductivity type are provided in part of an epitaxial layer of the opposite conductivity type on a more highly conductive substrate, the source fingers are short-circuited to the substrate, a gate on an insulating layer on the epitaxial layer is provided between the source and drain fingers, and a drain electrode which is interdigitated with the gate is provided to contact said drain fingers.
The invention further relates to a method of manufacturing this transistor.
In a paper entitled "Si UHF MOS High-power FET" on pages 733 and 734 of IEEE Transactions on Electron Devices, November 1974, there is disclosed a method of manufacturing an insulated-gate field-effect transistor for high frequency and high power operation. In this method interdigitated source and drain fingers of one conductivity type are provided in part of an epitaxial layer of the opposite conductivity type on a more highly conductive substrate; the source fingers are short-circuited to the substrate; a gate on an insulating layer on the epitaxial layer is provided between the source and drain fingers, and a drain electrode which is interdigitated with the gate is provided to contact said drain fingers. An advantage of such a transistor is that the source electrode can be provided by a connection to the back face of the substrate, for example on a copper heat sink. This permits the interdigitation off the gate and drain electrode to be uncomplicated by the source electrode, and is especially useful when the transistor is incorporated in the circuit in a common-source configuration.
However, the known method described in the IEEE Transactions paper has several disadvantages. The source-fingers are short-circuited to the substrate by a deep diffusion of highly-doped "pipes" which are of the same conductivity type as both the substrate (p+) and the p-type epitaxial layer. These p+ pipes are driven completely through the p-type epitaxial layer to contact the substrate. The interdigitated source and drain fingers (n+) are then provided by diffusion so that the source fingers overdope edge parts of the p+-types at the surface of the epitaxial layer. Subsequently an aluminum electrode pattern is formed comprising the interdigitated gate and drain electrodes as well as electrodes which short-circuit the n+ source fingers to the p+ pipes at the surface of the epitaxial layer.
Because the p+ pipes must be locally overdoped at the surface of the epitaxial layer by the n+ source fingers, the surface-doping concentration of the p+ pipes is restricted, and so the diffused doping concentration of the pipes where they approach the substrate is even smaller. This restriction on the doping concentration of the p+ pipes can cause significant series resistance for the source connection and so can result in significant negative feedback and reduced gain for the transistor when used in a grounded source configuration.
Because the acceptor dopant forming the p+ pipes diffuses laterally while being driven through the epitaxial layer, the resulting pipes can be wide and occupy a large surface area within the interdigitated geometry, particularly with thick epitaxial layers.
The aluminum electrode pattern is provided after the source and drain diffusion, and this is necessary to short-circuit the source fingers to the p+ pipes. It results in an aluminum gate, whereas for some applications a polycrystalline silicon gate may be desirable. It also results in the need for an alignment step between, on the one hand, a photo-mask used to define the electrode pattern and, on the other hand, the channel defined by the previously-provided n-type source and drain fingers. However, for good high frequency performance it is desirable to minimize the overlap capacitance of the gate with the source and drain fingers. Thus, it is desirable to use a self-aligned process in which the gate masks the channel area during the source and drain doping step. Modification of the method described in the IEEE Transactions paper so as to use a self-aligned process is hampered by the additional need which that method imposes of masking the source doping over the p+ pipes so as to terminate at the surface of the epitaxial layer the p-n junctions which are to be short-circuited.